Ok, Last time we have talk about what is a JTAG. This time we are going to talk about how JTAG works?

Control JTAG from PC

Simply we can use a “JTAG cable” to control a JTAG bus form a PC, it is just a way to control JTAG signals from PC. Normally, JTAG cables can be connect to your PC via Parallel port(Printer Port), USB port or Ethernet Port. The simplest JTAG cables are the Parallel port JTAG cables.

The Parallel Port
A parallel port is a twelve bits output and five bit input port from PC. But as we talk early, JTAG requires a one bit input and three bit output. So we can easily use a parallel port.

The JTAG TAP controller

From the last post, we learn that PC – JTAG connection will be as shown bellow.

 http://www.fpga4fun.com/JTAG2.html

As you can see on above figure, there are 4 signals (TDI, TDO, TMS, TCK).

TCK
TCK is the clock signal of the JTAG. This is help to synchronous the other JTAG signals (TDI, TDO, TMS). TCK is a rising edge toggle clock signal.

TMS
So, in each JTAG IC, there is a JTAG TAP controller. The TAP controller is mainly a state machine with 16 states. TMS signal controll the TAP controller. The TMS signal is connected parallel to each IC. Therefore, every TAP controller work at same time same state.

This figure shows TAP controller state machine,

  http://www.fpga4fun.com/JTAG2.html


The TAP controllers of a JTAG chain should always be at same state to JTAG to work properly. But it may not sync after power up. But, no matter what, if TMS stay in logic “1” for five clocks, a TAP controller goes back to the state “TEST-LOGIC-RESET”. This is use to sync the TAP controllers.

TDI and TDO

So at the moment, we have an idea about how to change state. We can use the most important JTAG states, “Shift-DR” and “Shift-IR”.

 http://www.fpga4fun.com/JTAG2.html

Shift-DR and Shift-IR are in combination with TDI and TDO lines.

Shift-IR
The term IR means “Instruction Register”. So, on each IC there is a IR. Each IC has there own possible instructions to write values on this register. You can write any value on that corresponds to what you wand to do with JTAG. For every IC, the length on the IR is not the same and it can be loaded through the TDI and TDO pins.

  http://www.fpga4fun.com/JTAG2.html

So, in this figure, we can see CPU has 5bit IR and FPGA has 10 bit IR. Therefore the IR registers chain has 15 bits. We can load IR values from the PC. For that you have to make sure the PC has TAP controllers in Shift-IR state and then send 15bits through TDI. The first 10 bits goes to FPGA and then the last 5 bits goes to CPU. If you sent more than 15 bits, then it starts receiving back what it sent on TDO.

According to the length of the IR registers, the number of instructions can be vary. But most of them are not often uesed. BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE are few mandatory instructions which JTAG has. To get the list of possible IR values, check the Datasheet of each IC.

Shift-DR
Each TAP controller has only one IR register. But there are multiple DR registers. Also, the DR registers are similar to the IR registers. The bits setting is in same way, but instead of Shift-IR, you should use Shift-DR. Each IR value will select different DR register.

So, up to now, I guess you have some idea about how this JTAG works… 🙂

references: http://www.fpga4fun.com/JTAG2.html

***Please note that all of the content on this post was originally published on champlnx.blogspot.com. We have migrated these posts to www.champlnx.com for your convenience and continued access.

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